Return to the SSTL specifications of Draft 1. 3 that describe these levels allow voltages well above 5V, but I don't know of any 1. MAU – Medium attachment unit. Calibration 8. You are required to use an external PHY device to. USXGMII Subsystem. The RGMII interface has been designed in accordance with the standards and specifications agreed in theThe present clauses in 802. Optional 802. TOD. 3 10 Gbps Ethernet standard. 3 Plenary, HSSG meeting, Atlanta, GA 11 10G Service interfaces XGMII is standardized instantiation of PCS interface (Clause 46) XAUI is standardized instantiation of XGMII Extender (Clause 47) In practical implementations physical interface between MAC and PHY XSBI is an optional physical instantiation of PMA service interface10-Gbps Ethernet MAC MegaCore Function user guide ›. all of the specification regarding the MII interface. 5Gb/s 8B/10B encoded - 3. Features 1. Designed to meet the USXGMII specification EDCS-1467841 revision 1. Abstract: 88X2040-BAN xGMII to rj45 phy marvell IEEE 946 motherboard Text: packets through the XAUI PCS soft IP and the LatticeECP3 XAUI PCS to the Marvell 88X2040 device. Resetting Transceiver Channels 5. 8V devices whose MDC/MDIO ports can withstand this without blowing a hole in the oxide. Notably, MII 370 is an interface capable of providing two-way communication between MAC device 350 and PHY device 360. XGMII Signals Signal Name Direction Width. 0 > 2. The objectives of the five workstreams are the following: M-HPM (Host Processor Modules) Workstream which involves three specifications: M-FLW (FulL Width HPM) Specify the requirements of a Full Width Host Processor Module (HPM). However, if the XGMII is not implemented, a conforming implementation must behave functionally as though the RS and XGMII were present. by clicking “i agree” or otherwise using or copying the relevant amba specification you indicate that you agree to be bound by all the terms of this licence. Features 6. 1. What i want to do is i want to feed the PCS with xgmii_tx signals, connect the txn/txp to rxn/rxp respectively and monitor the xgmii_rx signals whether they are the same as xgmii_tx. XGMII & XAUI Relationship to ISO/IEC Open Systems Interconnection (OSI) Reference Model & IEEE 802. However, the Altera implementation uses a wider bus interface in connecting a. Inter-Packet Gap Generation and Insertion 4. Reference HSTL at 1. 0 5 Network Controller Sideband Interface (NC-SI) 6 Specification 7 Document Type: Specification 8 Document Status: DMTF Standard 9 Document Language: EThe IEEE 802. 0 > 2. In order to connect a 10-Gigabit Ethernet MAC to an off-chip PHY device, an XGMII inter-face is used. Release Information 2. Configuration of the core is done through a configuration vector. Because of this,. It can be replaced by a resistor-capacitor combination, both of package size 0603. It provides high-speed, bi-directional, point-to-point data transmissions with up to 12. For D1. Arria V soft PCS does not support the XGMII interface to the MAC/RS as defined in the IEEE 802. 5GPII Word For off chip stuff, these days nobody uses XGMII, it's either XAUI (4x3. 5. Resource Utilization 3. 5. 6. Return to the SSTL specifications of Draft 1. The XgmiiSource and XgmiiSink classes can be used to drive, receive, and monitor XGMII traffic. The 10GBASE-X PCS provides services to the XGMII in a manner analogous to how the 1000BASE-X PCS provides services to the 1000 Mb/s GMII. The RGMII interface can be either a MAC interface or a media interface. Operating Speed and Status Signals XAUI is standardized instantiation of XGMII Extender (Clause 47) In practical implementations physical interface between MAC and PHY XSBI is an optional physical instantiation of PMA service interface for 10GBASE-R and 10GBASE-W (Clause 51) 16-bit bidirectional interface with source synchronous clock The XGMII interface, specified by IEEE 802. 3-2005 Clause 46) and I'm really surprised because it mentions a 32b data width for a frequency of 156. Configuration Registers 6. Resource Utilization 3. The XGMII Controller interface block interfaces with the Data rate adaptation block. 16. This document provides the technical specification for the Non-Real-Time RAN Intelligent Controller (Non-RT RIC) architecture. The subsidized sponsorship of standards via the IEEE GET Program helps expand the global reach of technical knowledge developed by industry, accelerates adoption of IEEE standards, contributes to an open knowledge community, promulgates open information exchange to foster innovation, and connects the IEEE brand with the development of. 3-2005. Mark as New; Bookmark; Subscribe; Mute; Subscribe to RSS Feed;The interface between the PCS and the RS is the XGMII as specified in Clause 46. 1. 2V HSTL signal pair to support low-power mode for each MIPI clock or data lane. USGMII provides flexibility to add new features while maintaining backward compatibility. 10GbEは 1GbE に続く通信速度を持つプロトコルとして開発され、最初の規格は 2002年 6月 に IEEE 802. If anybody is interested to see this document please go to FC web site at and search for doc 99-251v3. Georg Pauwen. Includes MAC modules for gigabit and 10G, a 10G PCS/PMA PHY module, and a 10G combination. 5G/5G/10G Multi-rate PHY. 8. 6. 1: XGMII (Clause 46) - Logical o 32-bit DDR TXD, 4-bit TXC and TX_CLK o 32-bit DDR RXD, 4-bit RXC and RX_CLK XGXS (Clause 47) – XAUI Electrical Spec (PMA) o 4 SERDES TX and 4 SERDES RX (PCS 8B/10B) @ 3. Serial-GMII Specification The Serial Gigabit Media Independent Interface (SGMII) is designed to satisfy the following requirements: • Convey network data and port speed between a 10/100/1000 PHY and a MAC with significantly less signal pins than required for GMII. Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. 49. - XGMII Interface (64-bit single clock edge) - POS-L3 like Interface for core logic side. 18. MDI. So to test initially I taken Example design of PCS/PMA IP and there I altered 1) ctl_loopback bit 1-> 0 (not setting in loop back) . to the PCS synchronization specification. Designed to meet the USXGMII specification EDCS-1467841 revision 1. 4. Implements 802. 3ba specifications and verifies MAC-to-PHY layer interfaces of designs with a 100G Ethernet interface CGMII. Same thing applies to TXC. It would > be a shame for TF ballot to be delayed because of the absence of XGMII > electricals. 44. Operating Speed and Status Signals The XAUI PHY uses the XGMII interface to connect to the IEEE802. The following features are supported in the 64b6xb: Fabric width is selectable. 8. 3 is used as the interface between an Ethernet physical layer device and a media access controller. 3. Features. The F-tile 1G/2. 5 volts per EIA/JESD8-6 and select from the options > within that specification. XAUI and XGMII Layers Section Content Transceiver Datapath in a XAUI Configuration XAUI Supported Features Transceiver Clocking and Channel Placement. The Serial Gigabit Media Independent Interface ( SGMII) is a sequel of MII, a standard interface used to connect an Ethernet MAC-block to a PHY. 2 Physical Medium Attachment (PMA) sublayerIs it possible to have the USXGMII specification, and any technical description. 3125 Gbit/s) • Data throughput is reduced: • inter-frame gaps are increased through extended operation of MPCP, which accounts for FEC parity insertion • Extra IDLEs are deleted in PCS and used to insert FEC partiyText: PHY devices via 10-Gbps media independent interface (XGMII) or 10-Gbps attachment unit interface (XAUI) Management data input/output. FPGA. 1. Table 1. mode, all the interface pins of 4 CPs in a cluster can be combined and used together to implement an 8-bit interface required by GMII. 10 Gigabit Ethernet MAC The 10 Gigabit Ethernet MAC core connects to the PHY layer through an external XGMII. Configuration Registers A. 10GBASE-KR is an Ethernet defined interface intended to enable 10. 1G/2. Each direction is independent and contains a 32-bit. Standardized. 5. However, the Altera implementation uses a wider bus interface in connecting a. 5. Interface (XGMII) 46. 3ae specification, the 10Gb Ethernet MAC (10 GMAC) core includes the option of either a parallel 10 Gigabit Media Independent Interface (XGMII) or a serial 10 Gigabit Attachment Unit Interface (XAUI). So to test initially I taken Example design of PCS/PMA IP and there I altered 1) ctl_loopback bit 1-> 0 (not setting in loop back) . For more information on aggregation mode, refer to the C-5 Network Processor Architecture Guide. 3 is used as the interface between an Ethernet physical layer device and a media access controller. we should see DLLP packets on the interface. This table lists all the Intel ® Arria 10 designs for Low Latency Ethernet 10G MAC Intel FPGA IP. 3125 Gbps serial line rate with 64B/66B encoding. Rockchip RK3588 datasheet. This module converts XGMII interface of XGMAC core to high speed serial interface needed by physical interface. This technology is called 10 Gigabit Ethernet Attachment Unit Interface, and is generally. 3-2012. The MAC TX also supports custom preamble in 10G operations. 3ae specification, the 10Gb Ethernet MAC (10 GMAC) core includes the option of either a parallel 10 Gigabit Media Independent Interface (XGMII) or a serial 10 Gigabit Attachment Unit Interface (XAUI). VIP Options. 0 that is designed to support both the device family using the IOD blocks used with GPIO or HSIO buffers. The XgmiiSource and XgmiiSink classes can be used to drive, receive, and monitor XGMII traffic. Intel® Stratix® 10 L-Tile/H-Tile Transceiver PHY Architecture 6. MAC. Figure 49–4 depicts the relationship and mapping interface. > > 1. Transceiver Status and Transceiver Clock Status Signals 6. 8. The most popular variant, 1000BASE-T, is defined by the IEEE 802. RGMII. ANSI TR/X3. When TCP/IP network is applied in. XLGMII is for 40G Interface. The XGMII interface, specified by IEEE 802. 3bz-2016 amending the XGMII specification to support operation at 2. 3-2008 standard and provides an interface between AHB/AXI Bus and the 10 Gigabit Media Independent Interface (XGMII) using a powerful 64-bit Scatter Gather DMA. The original single row of pins is compatible. 5M transfers/s) • PHY line rate is preserved (10. This includes not disabling Duty Cycle Correction for Virtex-II DCMs (as was done in XAPP606). 5GPII. The PHY layers are managed through an optional MDIO STA master interface. 1. About LL Ethernet 10G MAC 2. Register Map 7. 25 Mbps. The 10GBASE-X PCS provides all services required by the XGMII and in support of the 10GBASE-X PMA, including:The 64b/66b encoder is used to achieve DC balance and sufficient data transitions for clock recovery. 10GBASE-KR is an Ethernet defined interface intended to enable 10. 1: Enables USXGMII Auto-Negotiation, and automatically configures operating speed with link partner ability advertised during USXGMII Auto. It can also be used as a serial communication bus between the PowerQUICC™ MPC8313E and other peripherals such as through a. 3ab standard. Text: PHY devices via 10-Gbps media independent interface (XGMII) or 10-Gbps attachment unit interface (XAUI) Management data input/output. 2) enabled TX and RX bit in TX_ctrl and Rxctrl registers . 5G, 5G or 10GE over an IEEE 802. It was first defined by the IEEE 802. XGMII Encapsulation 4. The host application requests this xml file from the device and creates a register tree. AUTOSAR Interface. 10 Gigabit Attachment Unit Interface (XAUI / ˈ z aʊ i / ZOW-ee) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE) defined in Clause 47 of the IEEE 802. Several Physical Coding Sublayers known as 10GBASE-X, 10GBASE-R, and10GBASE-W are specified, as well as significant additional supporting material for a 10 GigabitMedia Independent Interface (XGMII), a 10 Gigabit Attachment. Xilinx has 10G/25G Ethernet Subsystem IP core. 265625 MHz. Where possible the PIPE specification references the PCI Express base specification specification rather than repeating its content. OSI Reference model layers. 25 Gbps line rate to achieve 10-Gbps data rate. Operating Speed and Status Signals. - Wishbone Interface for control. At the Tampa meeting I intend to propose that we just adopt the logic family that the XGMII uses (we might have to put a note in about termination schemes as the MDIO is multi-drop). Also, take a look at the timing diagrams in figures 46-5 and 46-6 on page 451 of IEEE. 3 Clause 46, is the main access to the 10G Ethernet physical layer. 125Gbps SERDES available at Between the MAC and the PHY is the XGMII, or 10 Gigabit Media Independent Interface. 11/13/2007 IEEE 802. We are using the Yocto Linux SDK. PCS) IP GT IP Serial. Several Physical Coding Sublayers known as 10GBASE-X, 10GBASE-R, and10GBASE-W are specified, as well as significant additional supporting material for a 10 GigabitMedia Independent Interface (XGMII), a 10 Gigabit Attachment. This specification, the Devicetree Specification (DTSpec), provides a complete boot program to client program interface definition, combined with minimum system requirements that facilitate the development of a wide variety of systems. 7. Xilinx has 10G/25G Ethernet Subsystem IP core. Please refer to PG210. Section Content Features Release Information LL. Figure 1. Check MAC PHY XGMII interface signals, no data sent out from MAC. 3az standard for Energy Efficient Ethernet. 3ae-2002 standard. XFI来源于XFP光模块标准的一部分，指的是连接ASIC芯片和XFP光模块的电气接口。. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and. 25 Gbps. Implements DTE XGXS, PHY XGXS and 10G BASE-X PCS in a single netlist. Statement on Forced Labor. Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor. 4. ) • 1. Headlight. 5V tolerance seems an unnecessary burden. This version supports HL7 V 2. 8. 8. Leverages DDR I/O primitives for the optional XGMII interface. e. Two XAUI link• Provide a physical layer specification supporting 100 Gb/s operation on a single wavelength capable of at least 80 km over a DWDM system. Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. The XGMII Controller interface block interfaces with the Data rate adaptation block. Signal. Software Architecture – AUTOSAR Defined Interfaces. Small Form-factor Pluggable (SFP) is a compact, hot-pluggable network interface module format used for both telecommunication and data communications applications. Features. XGMII Signals 6. There needs to be some way to allow alternate voltages for this interface and still be standards compliant. Uses two transceivers at 6. Resources Developer Site; Xilinx Wiki; Xilinx Github10 Gigabit Attachment Unit Interface ( XAUI / ˈzaʊi / ZOW-ee) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of. - XGMII Interface (64-bit single clock edge) - POS-L3 like Interface for core logic side - Wishbone Interface for control 2. 6 Functional block diagramHow is data transferred from the XAUI to the User interface? A8. Release Information 2. 5G, 5G, and 10G. A Makefile controls the simulation of the. 4. xMII. , the received data. The 10 Gigabit Media Independent Interface ( XGMII) is an interface standard that uses 72 data pins for both RX and TX. There are a total of 28 pins within a cluster, so each cluster has enough signals to implement one GMII interface. AUTOSAR Introduction - Part 2 21-Jul-2021. 3 that describe these levels allow voltages well above 5V, but I don't know of any 1. Avalon® Memory-Mapped Interface Signals 6. 7. N GMII Electrical Specification Page 8 IEEE P802. 5Gbps but can't find any reference design for it. The Full-Speed SDIO devices have a data transfer rate of over 100 Mb/second (10 MB/Sec). xgmii mdi up to 10 gbps clt – coax line terminal cnu – coax network unit mdi – medium dependent interface oam – operations, administration, & maintenance pcs – physical coding sublayer phy – physical layer device pma – physical medium attachment pmd – physical medium dependent xgmii – gigabit media independent interfaceFor D1. SerDes TX RX MII Serial Figure 5–1. Introduction. semi-formal notation to model SoS architectures with. version string. Unlike previous Ethernet. and added specification for 10/100 MII operation. AUTOSAR Interface. e. 1 XGMII Controller Interface 3. . 1 XGMII Interface The XGMII interface connects the Reconciliation Sublayer (RS) with the IP and allows transferring information to/from as defined in Clause 46. // Documentation Portal . The MAC core along with FIFO-core and SPI4/AXI-DMA enginesUSXGMII Subsystem. As measured from the input port xgmii_txd[63:0] of the transmitter side XGMII (until that data appears on the txdata pins on the internal transceiver interface on the transceiver interface), the latency through the core for the internal XGMII interface configuration in the transmit direction is four clk periods of the core input usrclk. The columns are divided into test parameters and results. XGMII Transmission 4. Avalon® -MM Interface Signals 6. 7. 4 SGMII interfaces mean 4 Tx and 4 Rx (8 in total) differential lines between the MAC and the PHY. Previous definition/implementations cover single (SGMII) and quad (QSGMII) options. 3 are described in terms of two primary interfaces Medium dependent interface (MDI) Media independent interface (MII) While the MDI is visible to the user, and usually tightly specified, the MII is often used simply as a convenient way to partition the physical layer specifications from the10 ギガビット イーサネット PCS/PMA (10GBASE-R) は、10 ギガビット イーサネット MAC への接続に XGMII インターフェイスを提供し、10. 1. LL Ethernet 10G MAC Operating Modes 1. So I don't think there's an easy way to connect 100G and 25G. 4)checked Jumper state. 10 Gigabit Ethernet (abbreviated 10GE, 10GbE, or 10 GigE) is a group of computer networking technologies for transmitting Ethernet frames at a rate of 10 gigabits per second. The inclusion of a XGMII means that several alternative PHY interfaces are readily supported, including XSBI (10 Gigabit Sixteen Bit Interface) and XAUI. 1 I inserted an editors note under an "Electrical interface" section as a place holder for an interface to be approved by the Task Force. MDI. The core is designed to work with the latest Virtex™ 6, Virtex 5 and Virtex 4 and Virtex II Pro and Spartan®-6 platform FPGAs and integrate seamlessly into the design flow. This spec provides some information about how the MAC could use the PIPE interface for various LTSSM states and Link states. (3) The WAN interface sublayer (WIS) implements the OC-192 framing and scrambling functions. Lane 0: xgmii_tx_control[0] Lane 1: xgmii_tx_control[1] Lane 2: xgmii_tx_control[2] Lane 3: xgmii_tx. The PHY side of the MAC implements the XLGMII or CGMII protocol as defined by the IEEE 802. 3 protocol and MAC specification to an operating speedof 10 Gb/s. RGMII to GMII converter provides the interface between a standard gigabit media independent interface (GMII) to RGMII conversion. I see three alternatives that would allow us to go forward to > TF ballot. 0. XGMII Data Interface Signals XGTMIICLK Output XGMII Transmit Clock (156. > > 1. Uses 7 series, Virtex 6, Virtex 5, Virtex 4, and Spartan 6 transceivers running 4 lanes at 3. The XGMII Controller interface block interfaces with the Data rate adaptation block. 1G/10GbE PHY Register Definitions 5. 3-2008 specification. 1. 5 Gb/s and 5 Gb/s as well as 10 Gb/s. According to the present embodiments, an Ethernet device having a Gigabit Media Independent Interface (GMII) coupled between its Media Access Control (MAC) layer and its physical (PHY) layer may enter a low power idle (LPI) mode (as defined by IEEE 802. ,Ltd E-mail: ip-sales@design-gateway. Status Signals 6. All transmit data and control signals. 25 Gbps. 1G/10GbE Control and Status Interfaces 5. Figure 46–1 shows the relationship of the RS and XGMII to the ISO/IEC (IEEE) OSI reference model. 10G USXGMII Ethernet PHY Configuration and Status Registers Description. 3 Clause 46, is the main access to the 10G Ethernet physical layer. 1 R2. XAUI is standardized instantiation of XGMII Extender (Clause 47) In practical implementations physical interface between MAC and PHY XSBI is an optional physical instantiation of PMA service interface for 10GBASE-R and 10GBASE-W (Clause 51) 16-bit bidirectional interface with source synchronous clock 10-Gbps Ethernet MAC MegaCore Function user guide ›. USGMII Specification. 3. 3 protocol and MAC specification to an operating speedof 10 Gb/s. 1 Voltage Mode Line DriverCollection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). 1for definition of SoS architectures lies in interface specification and a . Uses device-specific transceivers for the RXAUI interface. That being said, there may be an assumption made that a 10 Gb/s MAC/RS/XGMII implementationSerdes Lane A is connected to a Broadcom Ethernet switch on the board via SGMII. For D1. XGMIIはMACとPHYの間に位置する。RSはMACのビットシリアルプロトコルをPHYのパラレルエンコーディングに適合させる。 XGMIIの使用は必須ではないが、PCSはXGMIIを想定して仕様が定義されて. Features 2. XGMII Signals 6. 3. The optional WAN Interface Sublayer (WIS) part of th e 10GBASE-R standard is not implemented in this core. 0: Disables USXGMII Auto-Negotiation and manually configures the operating speed with the USXGMII_SPEED register. The _DSD object is a device specific configuration object, intended for firmware and software engineers implementing _DSD or designing. Implements DTE XGXS, PHY XGXS, and 10GBASE-X PCS in a single single encrypted HDL. For more information on aggregation mode, refer to the C-5 Network Processor Architecture Guide. 1G/10GbE GMII PCS Registers 5. 3 Clause 49 BASE-R physical coding sublayer/physical The 10GBASE-R PHY uses the XGMII interface to connect to the IEEE802. The XAUI 8b10b coding and SERDES. To interface MIPI CSI-2 D-PHY compliant I/O, the MAX 10 10M50 evaluation kit uses one 2. 0 to 1. 3-2018, Clause 46. Actually - I should amend this answer - XGMII isn't the correct protocol, I think I'm thinking of 10GBASE-R. It is primarily used to connect a video source to a display device such as a computer monitor. • No internal interface is super-rated, • XGMII rate is preserved (312. These specs were defined by the SFF MSA industry group. 3V supply voltages with the G-10b interface specifications to make up the GMII DC and AC characteristics. ÐÏ à¡± á> þÿ. xMII: MII – 100Mb/s Medium independent interface GMII. GMII TBI verification IP is developed by experts in Ethernet, who have. 3-2008 specification. The XGMII has an optional physical instantiation. > 3. However, Intel FPGAs do not comply with or support these interface specifications to directly interface with the required twisted-pair copper cables such as CAT-5/6/7. 145 400 Gb/s Attachment Unit Interface (400GAUI-n): A physical instantiation of the PMA service interface to extend the connection between 400 Gb/s capable PMAs over n lanes, used for chip-to-chip or chip-to-module interconnections. com N. PHY. Reconciliation Sublayer (RS) and XGMII. Transceiver Status and Transceiver Clock Status Signals 6. This guide and its associated documents provide recommendations on the use of the _DSD (Device Specific Data) object as defined in the ACPI Specification . Both Channel 0 & 1 PHY are UP with the rx_is_lockedtodata and rx_enh_blk_lock signals are high. Timing wise, the clock frequency could be multiplied by a factor of 10. The waveform below shows a DLLP packet. 25G-AUI is a single lane version of the C2C and C2M electrical interfaces defined in 802. 5 volts per EIA/JESD8-6 and select from the options > within that specification. An optional physical instantiation of the PMA service interface has also been defined (see Clause 51). reference design for SGMII at 2. 25MHz for direct interface to 10GBase-R, XAUI and RXUAI cores. com URL: Features. 5G, 5G, or 10GE data rates over a 10. (See IEEE Std 802. 125Gbps 10GBASE-R Clause 49 (IEEE 64B/66B PCS only) o No IEEE. ファイバーチャネル・オーバー・イーサネット. 4 11/18 Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100Support to extend the IEEE 802. In the 10G Ethernet segment, the Universal Serial 10G Media Independent Interface (USXGMII) IP core from Microchip enables building 10GBASE-R solutions on PolarFire. Getting Started 3. 1. 4. The Intel® Stratix® 10 devices contain a combination of GX, GXT, or GXE channels, in addition to the. 4. 2023年11月1日 閲覧。 ^ “QSGMII Specification” (2009年7月20日). 4. This is because the MAC is normally responsible for inserting the minimum Inter-frame Gap required on the transmitted XGMII data stream, and so the receiving XAUI would never see this situation; therefore, it is up to the user to provide appropriate simulation stimulus on the XGMII interface side of the XAUI Core that meets the IEEE specification. 1. 1G/2. Specifications; Documentation; Overview. There can be only abstract methods in the Java interface, not the method body. 3 Overview (Version 1. 25MHz. Core data width is the width of the data path connected to the USXGMII IP. All transmit data and control. About LL Ethernet 10G MAC x 1. Presentation. The system data width, that is, the width of the interface to the user logic, is c onfigured as 64 bits.